From dbcc8252e929fcb9e9d075dc61e6f82ce9ea46be Mon Sep 17 00:00:00 2001
From: Mohamed Gaber <donn@efabless.com>
Date: Mon, 25 Dec 2023 20:48:46 +0200
Subject: [PATCH] Ameliorate Warnings, PDN Generation, and the default design
(#2066)
~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)
---
.github/test_sets/get_test_matrix.py | 15 +-
Makefile | 6 +-
configuration/checkers.tcl | 3 -
configuration/floorplan.tcl | 4 -
configuration/general.tcl | 2 -
configuration/synthesis.tcl | 1 -
designs/ci | 2 +-
designs/spm/config.json | 28 +--
designs/spm/pin_order.cfg | 4 +-
designs/spm/src/spm.sdc | 2 +-
designs/spm/src/spm.v | 175 ++++++------------
designs/spm/verify/spm_tb.v | 106 +++++++++++
docs/source/reference/configuration.md | 17 +-
docs/source/tutorials/digital_guide.md | 12 +-
.../usage/advanced_power_grid_control.md | 8 +-
docs/source/usage/chip_integration.md | 4 +-
docs/source/usage/hardening_macros.md | 4 +-
flow.tcl | 2 +-
scripts/config/init.py | 4 +-
scripts/openroad/common/pdn_cfg.tcl | 30 +--
scripts/openroad/irdrop.tcl | 9 +-
scripts/openroad/pdn.tcl | 4 +
scripts/tcl_commands/all.tcl | 106 +++++------
scripts/tcl_commands/floorplan.tcl | 2 +-
scripts/tcl_commands/sta.tcl | 9 +-
scripts/utils/utils.tcl | 8 +-
26 files changed, 308 insertions(+), 259 deletions(-)
create mode 100644 designs/spm/verify/spm_tb.v
diff --git a/.github/test_sets/get_test_matrix.py b/.github/test_sets/get_test_matrix.py
index ae9a5218..66ebb967 100755
--- a/.github/test_sets/get_test_matrix.py
+++ b/.github/test_sets/get_test_matrix.py
@@ -40,10 +40,21 @@ TEST_SETS_FILE = os.path.join(__dir__, "test_sets.yml")
)
@click.argument("test_sets", nargs=-1)
def main(scls, use_json, test_sets):
-
data_str = open(TEST_SETS_FILE).read()
data = yaml.safe_load(data_str)
- test_set_data = filter(lambda e: e["scl"] in scls and e["name"] in test_sets, data)
+
+ all_scls = set([e["scl"] for e in data])
+ selected_scls = set()
+ for pattern in scls:
+ if pattern.endswith("/"):
+ for scl in all_scls:
+ if scl.startswith(pattern):
+ selected_scls.add(scl)
+ else:
+ selected_scls.add(pattern)
+ test_set_data = filter(
+ lambda e: e["scl"] in selected_scls and e["name"] in test_sets, data
+ )
designs = list()
for test_set in list(test_set_data):
diff --git a/Makefile b/Makefile
index 1c8799cb..d24d487e 100644
--- a/Makefile
+++ b/Makefile
@@ -48,7 +48,7 @@ include ./dependencies/image_name.mk
TEST_DESIGN ?= spm
DESIGN_LIST ?= spm
QUICK_RUN_DESIGN ?= spm
-BENCHMARK ?= regression_results/benchmark_results/SW_HD.csv
+BENCHMARK ?= regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv
REGRESSION_TAG ?= TEST_SW_HD
FASTEST_TEST_SET_TAG ?= FASTEST_TEST_SET
EXTENDED_TEST_SET_TAG ?= EXTENDED_TEST_SET
@@ -171,10 +171,10 @@ venv/created: ./requirements.txt ./requirements_dev.txt ./requirements_lint.txt
DLTAG=custom_design_List
.PHONY: test_design_list fastest_test_set extended_test_set
-fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) fastest_test_set)
+fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) fastest_test_set)
fastest_test_set: DLTAG=$(FASTEST_TEST_SET_TAG)
fastest_test_set: test_design_list
-extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) extended_test_set)
+extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) extended_test_set)
extended_test_set: DLTAG=$(EXTENDED_TEST_SET_TAG)
extended_test_set: test_design_list
test_design_list:
diff --git a/configuration/checkers.tcl b/configuration/checkers.tcl
index c518b25c..491c7f2e 100755
--- a/configuration/checkers.tcl
+++ b/configuration/checkers.tcl
@@ -17,10 +17,7 @@ set ::env(QUIT_ON_ASSIGN_STATEMENTS) 0
set ::env(QUIT_ON_UNMAPPED_CELLS) 1
set ::env(QUIT_ON_SYNTH_CHECKS) 1
set ::env(SYNTH_CHECKS_ALLOW_TRISTATE) 1
-set ::env(LINTER_RELATIVE_INCLUDES) 1
set ::env(LINTER_INCLUDE_PDK_MODELS) 1
-set ::env(QUIT_ON_LINTER_WARNINGS) 0
-set ::env(QUIT_ON_LINTER_ERRORS) 1
# STA
set ::env(QUIT_ON_TIMING_VIOLATIONS) 1
diff --git a/configuration/floorplan.tcl b/configuration/floorplan.tcl
index 12c7e0b6..d7afca05 100755
--- a/configuration/floorplan.tcl
+++ b/configuration/floorplan.tcl
@@ -12,8 +12,6 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-set ::env(DESIGN_IS_CORE) 1
-
# Floorplan defaults
set ::env(FP_SIZING) relative
set ::env(FP_CORE_UTIL) 50
@@ -45,8 +43,6 @@ set ::env(TOP_MARGIN_MULT) 4
set ::env(LEFT_MARGIN_MULT) 12
set ::env(RIGHT_MARGIN_MULT) 12
-set ::env(FP_PDN_HORIZONTAL_HALO) 10
-set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
set ::env(FP_TAP_HORIZONTAL_HALO) 10
set ::env(FP_TAP_VERTICAL_HALO) $::env(FP_TAP_HORIZONTAL_HALO)
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1
diff --git a/configuration/general.tcl b/configuration/general.tcl
index b5eba730..adfaa051 100755
--- a/configuration/general.tcl
+++ b/configuration/general.tcl
@@ -15,7 +15,6 @@
# General Defaults
set ::env(CLOCK_PERIOD) "10.0"
set ::env(USE_GPIO_PADS) 0
-set ::env(RSZ_DONT_TOUCH_RX) "$^"
set ::env(RSZ_MULTICORNER_LIB) 1
set ::env(RSZ_DONT_TOUCH) ""
@@ -41,7 +40,6 @@ set ::env(RUN_IRDROP_REPORT) 1
## Signoff
set ::env(RUN_CVC) 1
-set ::env(PRIMARY_GDSII_STREAMOUT_TOOL) magic
### Netgen
set ::env(RUN_LVS) 1
diff --git a/configuration/synthesis.tcl b/configuration/synthesis.tcl
index 68f80694..67c66ca0 100755
--- a/configuration/synthesis.tcl
+++ b/configuration/synthesis.tcl
@@ -28,7 +28,6 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(SYNTH_ADDER_TYPE) "YOSYS"
set ::env(CLOCK_BUFFER_FANOUT) 16
set ::env(SYNTH_READ_BLACKBOX_LIB) 0
-set ::env(SYNTH_ELABORATE_ONLY) 0
set ::env(SYNTH_FLAT_TOP) 0
set ::env(IO_PCT) 0.2
set ::env(SYNTH_EXTRA_MAPPING_FILE) ""
diff --git a/designs/ci b/designs/ci
index 6fdb36a4..ec48b853 160000
--- a/designs/ci
+++ b/designs/ci
@@ -1 +1 @@
-Subproject commit 6fdb36a4afec4061b7011cf96944c0e6ce90c564
+Subproject commit ec48b853d4958b46f559562a31363e59e89216ef
diff --git a/designs/spm/config.json b/designs/spm/config.json
index 3c7715e8..4573909b 100644
--- a/designs/spm/config.json
+++ b/designs/spm/config.json
@@ -1,30 +1,30 @@
{
+ "//": "Basics",
"DESIGN_NAME": "spm",
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PERIOD": 10,
"CLOCK_PORT": "clk",
- "CLOCK_NET": "ref::$CLOCK_PORT",
- "FP_PDN_VOFFSET": 7,
- "FP_PDN_HOFFSET": 7,
- "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PNR_SDC_FILE": "dir::src/spm.sdc",
+ "SIGNOFF_SDC_FILE": "dir::src/spm.sdc",
+ "//": "PDN",
+ "FP_PDN_VOFFSET": 5,
+ "FP_PDN_HOFFSET": 5,
+ "FP_PDN_VWIDTH": 2,
+ "FP_PDN_HWIDTH": 2,
+ "FP_PDN_VPITCH": 30,
+ "FP_PDN_HPITCH": 30,
"FP_PDN_SKIPTRIM": true,
+ "//": "Pin Order",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "//": "Technology-Specific Configs",
"pdk::sky130*": {
"FP_CORE_UTIL": 45,
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
+ "CLOCK_PERIOD": 10,
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
"MAX_FANOUT_CONSTRAINT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
}
},
"pdk::gf180mcu*": {
diff --git a/designs/spm/pin_order.cfg b/designs/spm/pin_order.cfg
index 1e9c657a..bc5332bb 100644
--- a/designs/spm/pin_order.cfg
+++ b/designs/spm/pin_order.cfg
@@ -1,6 +1,6 @@
#N
@min_distance=0.1
-x.*
+a.*
#S
$1
@@ -10,5 +10,5 @@ rst
clk
#W
-p
y
+x
diff --git a/designs/spm/src/spm.sdc b/designs/spm/src/spm.sdc
index 4d778ceb..8a01d678 100644
--- a/designs/spm/src/spm.sdc
+++ b/designs/spm/src/spm.sdc
@@ -1,2 +1,2 @@
set_units -time ns
-create_clock [get_ports clk] -name core_clock -period 10
+create_clock [get_ports clk] -name core_clock -period 10
diff --git a/designs/spm/src/spm.v b/designs/spm/src/spm.v
index c7191b1b..42f8db80 100644
--- a/designs/spm/src/spm.v
+++ b/designs/spm/src/spm.v
@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// Copyright 2023 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -12,130 +12,61 @@
// See the License for the specific language governing permissions and
// limitations under the License.
-module spm(clk, rst, x, y, p);
- parameter size = 32;
- input clk, rst;
- input y;
- input[size-1:0] x;
- output p;
+// (Parameterized) Unsigned Serial/Parallel Multiplier:
+// - Multiplicand x (Input bit-serially)
+// - Multiplier a (All bits at the same time/Parallel)
+// - Product y (Output bit-serial)
+module spm #(parameter bits=32) (
+ input clk,
+ input rst,
+ input x,
+ input[bits-1: 0] a,
+ output y
+);
+ wire[bits: 0] y_chain;
+ assign y_chain[0] = 0;
+ assign y = y_chain[bits];
+
+ wire[bits-1:0] a_flip;
+ generate
+ for (genvar i = 0; i < bits; i = i + 1) begin : flip_block
+ assign a_flip[i] = a[bits - i - 1];
+ end
+ endgenerate
+
+ delayed_serial_adder dsa[bits-1:0](
+ .clk(clk),
+ .rst(rst),
+ .x(x),
+ .a(a_flip),
+ .y_in(y_chain[bits-1:0]),
+ .y_out(y_chain[bits:1])
+ );
- wire[size-1:1] pp;
- wire[size-1:0] xy;
-
- genvar i;
-
- CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
- generate for(i=1; i<size-1; i=i+1) begin
- CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
- end endgenerate
- TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));
-
-endmodule
-
-module TCMP(clk, rst, a, s);
- input clk, rst;
- input a;
- output reg s;
-
- reg z;
-
- always @(posedge clk or posedge rst) begin
- if (rst) begin
- //Reset logic goes here.
- s <= 1'b0;
- z <= 1'b0;
- end
- else begin
- //Sequential logic goes here.
- z <= a | z;
- s <= a ^ z;
- end
- end
endmodule
-module CSADD(clk, rst, x, y, sum);
- input clk, rst;
- input x, y;
- output reg sum;
-
- reg sc;
-
- // Half Adders logic
- wire hsum1, hco1;
- assign hsum1 = y ^ sc;
- assign hco1 = y & sc;
-
- wire hsum2, hco2;
- assign hsum2 = x ^ hsum1;
- assign hco2 = x & hsum1;
-
- always @(posedge clk or posedge rst) begin
- if (rst) begin
- //Reset logic goes here.
- sum <= 1'b0;
- sc <= 1'b0;
- end
- else begin
- //Sequential logic goes here.
- sum <= hsum2;
- sc <= hco1 ^ hco2;
+module delayed_serial_adder(
+ input clk,
+ input rst,
+ input x,
+ input a,
+ input y_in,
+ output reg y_out
+);
+ reg last_carry;
+ wire last_carry_next;
+ wire y_out_next;
+
+ wire g = x & a;
+ assign {last_carry_next, y_out_next} = g + y_in + last_carry;
+
+ always @ (posedge clk or negedge rst) begin
+ if (!rst) begin
+ last_carry <= 1'b0;
+ y_out <= 1'b0;
+ end else begin
+ last_carry <= last_carry_next;
+ y_out <= y_out_next;
end
end
endmodule
-
-
-/*
-
-module spm_tb;
-
- //Inputs
- reg clk;
- reg rst;
- reg [7: 0] x;
-
- reg[7:0] Y;
- reg[15:0] P;
-
- //Outputs
- wire p;
-
- reg[3:0] cnt;
-
- //Instantiation of Unit Under Test
- spm #(8) uut (
- .clk(clk),
- .rst(rst),
- .y(Y[0]),
- .x(x),
- .p(p)
- );
-
- always #5 clk = ~clk;
-
- always @ (posedge clk)
- if(rst) Y = -50;
- else Y <= {1'b0,Y[7:1]};
-
- always @ (posedge clk)
- if(rst) P = 0;
- else P <= {p, P[15:1]};
-
- always @ (posedge clk)
- if(rst) cnt = 0;
- else cnt <= cnt + 1;
-
- initial begin
- //Inputs initialization
- clk = 0;
- rst = 0;
- x = 50;
-
- //Reset
- #20 rst = 1;
- #20 rst = 0;
- #1000;
- $finish;
- end
-
-endmodule
-*/
diff --git a/designs/spm/verify/spm_tb.v b/designs/spm/verify/spm_tb.v
new file mode 100644
index 00000000..42607692
--- /dev/null
+++ b/designs/spm/verify/spm_tb.v
@@ -0,0 +1,106 @@
+// Copyright 2023 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module spm_tb;
+ localparam bits = 32;
+ reg clk;
+ reg rst;
+ reg load;
+ reg[bits-1:0] x;
+ reg[bits-1:0] a;
+
+ wire[bits-1:0] srx_value;
+ sreg #(bits) srx(
+ .clk(clk),
+ .rst(rst),
+ .direction(1'b1),
+ .serial_msb(1'b0),
+ .serial_lsb(1'b0),
+ .load(load),
+ .load_value(x),
+ .value(srx_value)
+ );
+
+ wire y;
+ wire [bits*2-1:0] y_value;
+ sreg #(bits * 2) sry(
+ .clk(clk),
+ .rst(rst),
+ .direction(1'b1),
+ .serial_msb(y),
+ .serial_lsb(1'b0),
+ .load(1'b0),
+ .load_value({(bits*2){1'b0}}),
+ .value(y_value)
+ );
+
+ spm dut(
+ .clk(clk),
+ .rst(rst),
+ .x(srx_value[0]),
+ .a(a),
+ .y(y)
+ );
+
+ always #1 clk = ~clk;
+
+ reg [bits*2-1:0] expected;
+
+ initial begin
+ $dumpvars(0, spm_tb);
+ for (integer i = 0; i < 20; i = i + 1) begin
+ clk = 0;
+ rst = 0;
+ load = 0;
+ x = $random;
+ a = $random;
+ expected = x * a;
+ #2;
+ load = 1;
+ rst = 1;
+ #2;
+ load = 0;
+ #2; // No useful bit at the first clock cycle
+ #(bits * 2 * 2); // 2 * bits * clock cycle duration
+ $display("%h * %h", x, a);
+ $display("expected %h, got %h (%s)", expected, y_value, expected==y_value ? "ok " : "err");
+ end
+ $finish;
+ end
+endmodule
+
+module sreg #(parameter width = 32) (
+ input clk,
+ input rst,
+ input direction, // 0 -> load from lsb side; 1 -> load from msb side
+ input serial_msb,
+ input serial_lsb,
+ input load,
+ input[width-1:0] load_value,
+ output[width-1:0] value
+);
+ reg[width-1:0] store;
+
+ assign value = store;
+
+ always @ (posedge clk or negedge rst) begin
+ if (!rst) begin
+ store <= {(width){1'b0}};
+ end else begin
+ store <= load ? load_value :
+ direction ? {serial_msb, store[width-1:1]}:
+ {store[width-2:0], serial_lsb};
+ end
+ end
+endmodule
diff --git a/docs/source/reference/configuration.md b/docs/source/reference/configuration.md
index 3e1e3e80..6fa60f3c 100644
--- a/docs/source/reference/configuration.md
+++ b/docs/source/reference/configuration.md
@@ -78,7 +78,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
|-|-|
| `SYNTH_AUTONAME` <a id="SYNTH_AUTONAME"></a> | Add a synthesis step to generate names for instances. This results in instance names that can be very long, but may be more useful than the internal names that are six digit numbers. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
| `SYNTH_BIN` <a id="SYNTH_BIN"></a> | The yosys binary used in the flow. <br> (Default: `yosys`) |
-| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: NONE) |
+| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: None) |
| `SYNTH_CLOCK_UNCERTAINTY` <a id="SYNTH_CLOCK_UNCERTAINTY"></a> | Specifies a value for the clock uncertainty/jitter for timing analysis. <br> (Default: `0.25`) |
| `SYNTH_CLOCK_TRANSITION` <a id="SYNTH_CLOCK_TRANSITION"></a> | Specifies a value for the clock transition /slew for timing analysis. <br> (Default: `0.15`) |
| `SYNTH_TIMING_DERATE` <a id="SYNTH_TIMING_DERATE"></a> | Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing. <br> (Default: `+5%/-5%`) |
@@ -107,7 +107,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
| Variable | Description |
|-|-|
| `STA_REPORT_POWER` <a id="STA_REPORT_POWER"></a> | Enables reporting power in sta. <br> (Default: `1`) |
-| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files. <br> (Default: NONE) |
+| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files. <br> (Default: None) |
| `STA_WRITE_LIB` <a id="STA_WRITE_LIB"></a> | Controls whether a timing model is written using OpenROAD OpenSTA after static timing analysis. This is an option as it in its current state, the timing model generation (and the model itself) can be quite buggy. <br> (Default: `1`) |
## Floorplanning (FP)
@@ -148,19 +148,20 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
| `FP_TAP_VERTICAL_HALO` <a id="FP_TAP_VERTICAL_HALO"></a> | Specify the vertical halo size around macros during tap insertion. The value provided is in microns. <br> (Default: set to the value of `FP_TAP_HORIZONTAL_HALO`) |
| `FP_PDN_HORIZONTAL_HALO` <a id="FP_PDN_HORIZONTAL_HALO"></a> | Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: `10`) |
| `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: set to the value of `FP_PDN_HORIZONTAL_HALO`) |
-| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
-| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: NONE)|
-| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
-| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
+| `FP_PDN_MULTILAYER` <a id="FP_PDN_MULTILAYER"></a> | Controls the layers used in the power grid. If set to `0` (Tcl)/`false` (JSON), only the lower, vertical layer will be used, which is useful when hardening a macro for integrating into a larger top-level design. <br> (Default: `1`)|
+| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: None)|
+| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
+| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
| `FP_DEF_TEMPLATE` <a id="FP_DEF_TEMPLATE"></a> | Points to the DEF file to be used as a template when running `apply_def_template`. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the `CURRENT_DEF`. |
| `VDD_NETS` <a id="VDD_NETS"></a> | Specifies the power nets/pins to be used when creating the power grid for the design. |
| `GND_NETS` <a id="GND_NETS"></a> | Specifies the ground nets/pins to be used when creating the power grid for the design. |
| `SYNTH_USE_PG_PINS_DEFINES` <a id="SYNTH_USE_PG_PINS_DEFINES"></a> | Specifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract `VDD_NETS` and `GND_NET` variables from the verilog, with the assumption that they will be order `inout vdd1, inout gnd1, inout vdd2, inout gnd2, ...`. |
| `FP_IO_MIN_DISTANCE` <a id="FP_IO_MIN_DISTANCE"></a> | The minmimum distance between the IOs in microns. <br> (Default: `3`) |
-| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a> | A configuration file passed to padringer, a padframe generator. <br> (Default: NONE) |
+| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a> | A configuration file passed to padringer, a padframe generator. <br> (Default: None) |
| `PDN_CFG` <a id="PDN_CFG"></a> | **Deprecated: Use `FP_PDN_CFG`**: Points to a PDN configuration file that describes how to construct the PDN in detail. |
| `FP_HORIZONTAL_HALO` <a id="FP_HORIZONTAL_HALO"></a> | **Deprecated: Use `FP_PDN_HORIZONTAL_HALO`**: Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns.|
| `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | **Deprecated: Use `FP_PDN_VERTICAL_HALO`**: Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. |
+| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | **Deprecated as even macros can have a full-stack PDN if core rings are used: New variable is `FP_PDN_MULTILAYER`** Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
| `FP_PDN_IRDROP` <a id="FP_PDN_IRDROP"></a> | **Removed: No point running it this early in the flow**: Enable calculation of power grid IR drop during PDN generation. |
### Deprecated I/O Layer variables
@@ -367,7 +368,7 @@ For more information on integrating macros and other relevant configuration vari
|Variable|Description|
|-|-|
| `RUN_IRDROP_REPORT` <a id="RUN_IRDROP_REPORT"></a> | Creates an IR Drop report using OpenROAD PSM. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
-| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | PSM loc file for power and ground nets. Variable should be provided as a json/tcl list or a space delimited tcl string as follows: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info.<br> (Default: NONE) |
+| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | Map of voltage source nets to OpenROAD PSM location files. Variable should be provided as a Tcl dict, i.e.: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info. <br> (Default: None) |
## Signoff
diff --git a/docs/source/tutorials/digital_guide.md b/docs/source/tutorials/digital_guide.md
index 6b2dc276..03a141f2 100644
--- a/docs/source/tutorials/digital_guide.md
+++ b/docs/source/tutorials/digital_guide.md
@@ -58,7 +58,7 @@ Modify the `config.json` to include following:
:language: json
```
-`DESIGN_IS_CORE` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
+`FP_PDN_MULTILAYER` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
`FP_PDN_CORE_RING` is set to `false` to disable a power ring around the macroblock.
@@ -136,7 +136,7 @@ Then add `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS` and `EXTRA_GDS_FILES` to the `co
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": true,
+ "FP_PDN_MULTILAYER": true,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
"EXTRA_GDS_FILES": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
@@ -156,7 +156,7 @@ This is a [known issue documented here](https://github.com/The-OpenROAD-Project/
The PDN straps will be routed in opposite directions.
In locations where the two routings cross each other,
-VIAs connecting the layers are added. When `DESIGN_IS_CORE` is set to `true` then higher layers (met5 in sky130) are used.
+VIAs connecting the layers are added. When `FP_PDN_MULTILAYER` is set to `true` then higher layers (met5 in sky130) are used.
If it is set to `false` then VIAs will be missing and you will get LVS issues.
### Verilog files
@@ -493,7 +493,7 @@ Fanout Cap Slew Delay Time Description
### Demo: Debugging LVS issues due to PDN issues
-Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESIGN_IS_CORE` to `false`.
+Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `FP_PDN_MULTILAYER` to `false`.
```
{
@@ -501,7 +501,7 @@ Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESI
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": false,
+ "FP_PDN_MULTILAYER": false,
"FP_ASPECT_RATIO": 2,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
@@ -589,7 +589,7 @@ The submacros are by default logically connected to `VPWR/VGND` power domain.
As can be seen, the PDN is missing the power straps in layer `met5`.
Therefore the layout, does not have connections to the submacro, while the net is logically connected.
-This is expected as it was disabled by setting `DESIGN_IS_CORE` to `false` above.
+This is expected as it was disabled by setting `FP_PDN_MULTILAYER` to `false` above.
Of course, reverting the change fixes this issue.
:::{note}
diff --git a/docs/source/usage/advanced_power_grid_control.md b/docs/source/usage/advanced_power_grid_control.md
index 000fb3da..530b852e 100644
--- a/docs/source/usage/advanced_power_grid_control.md
+++ b/docs/source/usage/advanced_power_grid_control.md
@@ -31,7 +31,7 @@ The first decision to make at the core level is the core ring. So first, you nee
<td>
```json
- "DESIGN_IS_CORE": true,
+ "FP_PDN_MULTILAYER": true,
"FP_PDN_CORE_RING": true,
"VDD_NETS": "vccd1 vccd2 vdda1 cdda2",
"GND_NETS": "vssd1 vssd2 vssa1 vssa2",
@@ -44,7 +44,7 @@ The first decision to make at the core level is the core ring. So first, you nee
<td>
```tcl
-set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_MULTILAYER) 1
set ::env(FP_PDN_CORE_RING) 1
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
@@ -198,7 +198,7 @@ To begin the configurations for your macro, you want to announce that the design
<td>
```json
- "DESIGN_IS_CORE": false,
+ "FP_PDN_MULTILAYER": false,
"FP_PDN_CORE_RING": false,
"RT_MAX_LAYER": "met4"
```
@@ -208,7 +208,7 @@ To begin the configurations for your macro, you want to announce that the design
<td>
```tcl
-set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_MULTILAYER) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(RT_MAX_LAYER) "met4"
```
diff --git a/docs/source/usage/chip_integration.md b/docs/source/usage/chip_integration.md
index 4963a9dc..757f82cb 100644
--- a/docs/source/usage/chip_integration.md
+++ b/docs/source/usage/chip_integration.md
@@ -99,7 +99,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
<td>
```json
- "DESIGN_IS_CORE": true,
+ "FP_PDN_MULTILAYER": true,
"FP_PDN_CORE_RING": true
```
@@ -108,7 +108,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
<td>
```tcl
- set ::env(DESIGN_IS_CORE) 1
+ set ::env(FP_PDN_MULTILAYER) 1
set ::env(FP_PDN_CORE_RING) 1
```
</td>
diff --git a/docs/source/usage/hardening_macros.md b/docs/source/usage/hardening_macros.md
index 57574e93..00638dd0 100644
--- a/docs/source/usage/hardening_macros.md
+++ b/docs/source/usage/hardening_macros.md
@@ -21,7 +21,7 @@ Click on any variable name listed in this document to get its usage information.
* [`VERILOG_FILES`](../reference/configuration.md#VERILOG_FILES)
* [`CLOCK_PORT`](../reference/configuration.md#CLOCK_PORT)
* [`CLOCK_PERIOD`](../reference/configuration.md#CLOCK_PERIOD)
-* [`DESIGN_IS_CORE`](../reference/configuration.md#DESIGN_IS_CORE) (You may leave it empty if true)
+* [`FP_PDN_MULTILAYER`](../reference/configuration.md#FP_PDN_MULTILAYER) (You may leave it empty if true)
So, for example:
@@ -44,7 +44,7 @@ set ::env(DESIGN_NAME) {spm}
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(CLOCK_PORT) {clk}
-set ::env(DESIGN_IS_CORE) {0}
+set ::env(FP_PDN_MULTILAYER) {0}
```
</td>
diff --git a/flow.tcl b/flow.tcl
index ff2dcb6d..710f19ad 100755
--- a/flow.tcl
+++ b/flow.tcl
@@ -395,7 +395,7 @@ puts "OpenLane $::env(OPENLANE_VERSION)"
if { [info exists ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION)] } {
puts "(with mounted scripts from $::env(OPENLANE_MOUNTED_SCRIPTS_VERSION))"
}
-puts "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors."
+puts "All rights reserved. (c) 2020-2023 Efabless Corporation and contributors."
puts "Available under the Apache License, version 2.0. See the LICENSE file for more details."
puts ""
diff --git a/scripts/config/init.py b/scripts/config/init.py
index 3ef9583e..a0015edf 100644
--- a/scripts/config/init.py
+++ b/scripts/config/init.py
@@ -72,7 +72,7 @@ def init_config(
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_PERIOD) "10.0"
- set ::env(DESIGN_IS_CORE) {{1}}
+ set ::env(FP_PDN_MULTILAYER) {{1}}
set tech_specific_config "$::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl"
if {{ [file exists $tech_specific_config] == 1 }} {{
@@ -93,7 +93,7 @@ def init_config(
"VERILOG_FILES": verilog_arg,
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": True,
+ "FP_PDN_MULTILAYER": True,
},
indent=4,
sort_keys=False,
diff --git a/scripts/openroad/common/pdn_cfg.tcl b/scripts/openroad/common/pdn_cfg.tcl
index b93ba9fb..85a5ef28 100644
--- a/scripts/openroad/common/pdn_cfg.tcl
+++ b/scripts/openroad/common/pdn_cfg.tcl
@@ -43,10 +43,7 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary
-# Assesses whether the design is the core of the chip or not based on the
-# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
-if { $::env(DESIGN_IS_CORE) == 1 } {
- # Used if the design is the core of the chip
+if { $::env(FP_PDN_MULTILAYER) == 1 } {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
@@ -75,7 +72,6 @@ if { $::env(DESIGN_IS_CORE) == 1 } {
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
} else {
- # Used if the design is a macro in the core
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
@@ -88,7 +84,7 @@ if { $::env(DESIGN_IS_CORE) == 1 } {
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
- -starts_with POWER
+ -starts_with POWER -extend_to_core_ring
}
# Adds the standard cell rails if enabled.
@@ -108,12 +104,22 @@ if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
- add_pdn_ring \
- -grid stdcell_grid \
- -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
- -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
- -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
- -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
+ if { $::env(FP_PDN_MULTILAYER) == 1 } {
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
+ } else {
+ throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
+ # add_pdn_ring \
+ # -grid stdcell_grid \
+ # -layers "$::env(FP_PDN_VERTICAL_LAYER)" \
+ # -widths "$::env(FP_PDN_CORE_RING_VWIDTH)" \
+ # -spacings "$::env(FP_PDN_CORE_RING_VSPACING)" \
+ # -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET)"
+ }
}
define_pdn_grid \
diff --git a/scripts/openroad/irdrop.tcl b/scripts/openroad/irdrop.tcl
index ab0fab67..d7874dec 100644
--- a/scripts/openroad/irdrop.tcl
+++ b/scripts/openroad/irdrop.tcl
@@ -26,12 +26,19 @@ if { [info exists ::env(VSRC_LOC_FILES)] } {
analyze_power_grid {*}$arg_list
}
} else {
- foreach net "$::env(VDD_NETS) $::env(GND_NETS)" {
+ foreach net "$::env(VDD_NETS)" {
set arg_list [list]
lappend arg_list -net $net
lappend arg_list -outfile $::env(_tmp_save_rpt_prefix)-$net.rpt
analyze_power_grid {*}$arg_list
}
+ foreach net "$::env(GND_NETS)" {
+ set arg_list [list]
+ lappend arg_list -net $net
+ lappend arg_list -outfile $::env(_tmp_save_rpt_prefix)-$net.rpt
+ set_pdnsim_net_voltage -net $net -voltage 0
+ analyze_power_grid {*}$arg_list
+ }
}
diff --git a/scripts/openroad/pdn.tcl b/scripts/openroad/pdn.tcl
index 7fe6e27c..8732dace 100644
--- a/scripts/openroad/pdn.tcl
+++ b/scripts/openroad/pdn.tcl
@@ -16,6 +16,10 @@ source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
read
# load the grid definitions
+
+## For backwards compat
+set ::env(DESIGN_IS_CORE) $::env(FP_PDN_MULTILAYER)
+
if {[catch {source $::env(FP_PDN_CFG)} errmsg]} {
puts stderr $errmsg
exit 1
diff --git a/scripts/tcl_commands/all.tcl b/scripts/tcl_commands/all.tcl
index 8d4ed69e..a8bec1f9 100755
--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -400,6 +400,42 @@ proc load_overrides {args} {
}
}
+proc handle_config_var_deprecation {args} {
+ # DEPRECATED CONFIGS
+ ## PDK
+ handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
+ handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
+ handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
+ handle_deprecated_pdk_config WIRE_RC_LAYER DATA_WIRE_RC_LAYER
+ handle_deprecated_pdk_config WIRE_RC_LAYER CLOCK_WIRE_RC_LAYER
+
+ ## Flow
+ handle_diode_insertion_strategy
+
+ handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY 0
+
+ handle_deprecated_config VERILATOR_RELATIVE_INCLUDES LINTER_RELATIVE_INCLUDES 1
+
+ handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO 10
+ handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO $::env(FP_PDN_HORIZONTAL_HALO)
+
+ handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
+ handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX "$^"
+
+ handle_deprecated_config RCX_SDC_FILE SIGNOFF_SDC_FILE
+ handle_deprecated_config PRIMARY_SIGNOFF_TOOL PRIMARY_GDSII_STREAMOUT_TOOL "magic"
+
+ ### Checkers/Quitting
+ handle_deprecated_config QUIT_ON_VERILATOR_WARNINGS QUIT_ON_LINTER_WARNINGS 0
+ handle_deprecated_config QUIT_ON_VERILATOR_ERRORS QUIT_ON_LINTER_ERRORS 1
+
+ ### Flow Control
+ handle_deprecated_config RUN_VERILATOR RUN_LINTER 1
+
+ ### PDN
+ handle_deprecated_config DESIGN_IS_CORE FP_PDN_MULTILAYER 1
+}
+
proc prep {args} {
set ::env(timer_start) [clock seconds]
TIMER::timer_start
@@ -616,64 +652,6 @@ proc prep {args} {
set ::env(OPENLANE_VERBOSE) $arg_values(-verbose)
- # DEPRECATED CONFIGS
- ## PDK
- handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
- handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
- handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
- handle_deprecated_pdk_config WIRE_RC_LAYER DATA_WIRE_RC_LAYER
- handle_deprecated_pdk_config WIRE_RC_LAYER CLOCK_WIRE_RC_LAYER
-
- ## Flow
- handle_diode_insertion_strategy
-
- handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY
-
- handle_deprecated_config VERILATOR_RELATIVE_INCLUDES LINTER_RELATIVE_INCLUDES
-
- handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO
- handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO
-
- handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
- handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX
-
- handle_deprecated_config RCX_SDC_FILE SIGNOFF_SDC_FILE
- handle_deprecated_config PRIMARY_SIGNOFF_TOOL PRIMARY_GDSII_STREAMOUT_TOOL
-
- ### Checkers/Quitting
- handle_deprecated_config CHECK_ASSIGN_STATEMENTS QUIT_ON_ASSIGN_STATEMENTS
- handle_deprecated_config CHECK_UNMAPPED_CELLS QUIT_ON_UNMAPPED_CELLS
- handle_deprecated_config QUIT_ON_VERILATOR_WARNINGS QUIT_ON_LINTER_WARNINGS
- handle_deprecated_config QUIT_ON_VERILATOR_ERRORS QUIT_ON_LINTER_ERRORS
-
- ### Flow Control
- handle_deprecated_config CLOCK_TREE_SYNTH RUN_CTS
- handle_deprecated_config TAP_DECAP_INSERTION RUN_TAP_DECAP_INSERTION
- handle_deprecated_config RUN_ROUTING_DETAILED RUN_DRT
- handle_deprecated_config FILL_INSERTION RUN_FILL_INSERTION
- handle_deprecated_config RUN_VERILATOR RUN_LINTER
-
- ### PDN
- handle_deprecated_config FP_PDN_RAILS_LAYER FP_PDN_RAIL_LAYER
- handle_deprecated_config FP_PDN_UPPER_LAYER FP_PDN_HORIZONTAL_LAYER
- handle_deprecated_config FP_PDN_LOWER_LAYER FP_PDN_VERTICAL_LAYER
- handle_deprecated_config PDN_CFG FP_PDN_CFG
-
- ### GLB_RT -> GRT (Document using ‡)
- handle_deprecated_config GLB_RT_ALLOW_CONGESTION GRT_ALLOW_CONGESTION
- handle_deprecated_config GLB_RT_OVERFLOW_ITERS GRT_OVERFLOW_ITERS
- handle_deprecated_config GLB_RT_ANT_ITERS GRT_ANT_ITERS
- handle_deprecated_config GLB_RT_ESTIMATE_PARASITICS GRT_ESTIMATE_PARASITICS
- handle_deprecated_config GLB_RT_MAX_DIODE_INS_ITERS GRT_MAX_DIODE_INS_ITERS
- handle_deprecated_config GLB_RT_OBS GRT_OBS
- handle_deprecated_config GLB_RT_ADJUSTMENT GRT_ADJUSTMENT
- handle_deprecated_config GLB_RT_MACRO_EXTENSION GRT_MACRO_EXTENSION
- handle_deprecated_config GLB_RT_LAYER_ADJUSTMENTS GRT_LAYER_ADJUSTMENTS
-
- ### Spelling (No need to document)
- handle_deprecated_config CELL_PAD_EXECLUDE CELL_PAD_EXCLUDE
- handle_deprecated_config SYNTH_CLOCK_UNCERTAINITY SYNTH_CLOCK_UNCERTAINTY
-
#
############################
# Prep directories and files
@@ -706,6 +684,10 @@ proc prep {args} {
# file mkdir works like shell mkdir -p, i.e., its OK if it already exists
file mkdir $::env(RESULTS_DIR) $::env(TMP_DIR) $::env(LOGS_DIR) $::env(REPORTS_DIR)
+ # must be called after RUN_DIR is created so deprecation warnings are
+ # properly set to file
+ handle_config_var_deprecation
+
set run_subfolder_structure [list \
synthesis\
floorplan\
@@ -1247,15 +1229,15 @@ proc run_antenna_check {args} {
}
proc run_irdrop_report {args} {
+ if { ![info exists ::env(VSRC_LOC_FILES)] } {
+ puts_warn "VSRC_LOC_FILES was not given a value, which may make the results of IR drop analysis inaccurate. If you are not integrating a top-level chip for manufacture, you may ignore this warning, otherwise, see the documentation for VSRC_LOC_FILES."
+ }
+
increment_index
TIMER::timer_start
set log [index_file $::env(signoff_logs)/irdrop.log]
puts_info "Creating IR Drop Report (log: [relpath . $log])..."
- if { ![info exists ::env(VSRC_LOC_FILES)] } {
- puts_warn "VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate."
- }
-
set rpt [index_file $::env(signoff_reports)/irdrop]
set ::env(_tmp_save_rpt_prefix) $rpt
diff --git a/scripts/tcl_commands/floorplan.tcl b/scripts/tcl_commands/floorplan.tcl
index 71714f85..51952388 100755
--- a/scripts/tcl_commands/floorplan.tcl
+++ b/scripts/tcl_commands/floorplan.tcl
@@ -88,7 +88,7 @@ proc init_floorplan {args} {
set ::env(FP_PDN_VPITCH) [lindex $adjusted_values 2]
set ::env(FP_PDN_HPITCH) [lindex $adjusted_values 3]
- puts_warn "Current core area is too small for the power grid settings chosen. The power grid will be scaled down."
+ puts_warn "Current core area is too small for the power grid settings chosen. The power grid was scaled down to an offset of 1/8 the core width and height and a pitch of 1/4 the core width and height."
}
}
diff --git a/scripts/tcl_commands/sta.tcl b/scripts/tcl_commands/sta.tcl
index 1fb3e06a..029225ee 100644
--- a/scripts/tcl_commands/sta.tcl
+++ b/scripts/tcl_commands/sta.tcl
@@ -79,6 +79,7 @@ proc run_sta {args} {
proc blackbox_modules_check {file_path} {
set fp [open $file_path r]
set file_path [read $fp]
+ set modules [list]
set ignore_patterns "$::env(FILL_CELL) $::env(DECAP_CELL) $::env(FP_WELLTAP_CELL)"
foreach line [split $file_path "\n"] {
if { [regexp {module\s+(\S+)\s+not\s+found} $line match first_group] } {
@@ -89,10 +90,16 @@ proc run_sta {args} {
}
}
if { $ignored != 1 } {
- puts_warn "Module $first_group blackboxed during sta"
+ lappend modules $first_group
}
}
}
+ if { [llength $modules] > 0 } {
+ puts_warn "The following modules were black-boxed for STA as there was no timing information found:"
+ foreach {m} $modules {
+ puts_warn "\t* $m"
+ }
+ }
close $fp
}
diff --git a/scripts/utils/utils.tcl b/scripts/utils/utils.tcl
index c101610e..5fe79e44 100755
--- a/scripts/utils/utils.tcl
+++ b/scripts/utils/utils.tcl
@@ -21,9 +21,9 @@ proc throw_error {} {
}
}
-proc handle_deprecated_config {old new} {
+proc handle_deprecated_config {old new {default ""}} {
if { [info exists ::env($old)] } {
- puts_warn "$old is now deprecated; use $new instead."
+ puts_warn "The variable name $old was renamed to $new\. Update your configuration file."
if { ! [info exists ::env($new)] } {
set ::env($new) $::env($old)
@@ -32,6 +32,10 @@ proc handle_deprecated_config {old new} {
puts_err "Conflicting values of $new and $old; please remove $old from your design configurations"
throw_error
}
+ } elseif { [info exists ::env($new)] } {
+ # That's fine
+ } elseif { $default != "" } {
+ set ::env($new) $default
}
}
--
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