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Unverified Commit 892d791f authored by Kareem Farid's avatar Kareem Farid Committed by GitHub
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Check if `CLOCK_PORT` is found in the design (#2074)


+ Add check for whether the ports listed under `CLOCK_PORT` in fact exist in the top-level module
- Remove misleading CTS log print

Co-authored-by: default avatarMohamed Gaber <donn@efabless.com>
parent a3b780f4
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......@@ -33,4 +33,4 @@
"MAX_FANOUT_CONSTRAINT": 4,
"PL_TARGET_DENSITY": 0.5
}
}
\ No newline at end of file
}
# Copyright 2023 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import json
import click
@click.command()
@click.option("--netlist-in", required=True, help="JSON netlist")
@click.option("--top", required=True, help="Top module")
@click.argument("clock_ports", nargs=-1)
def main(netlist_in, top, clock_ports):
netlist = json.load(open(netlist_in, encoding="utf8"))
top_module = netlist["modules"][top]
ports = top_module["ports"]
for clock_port in clock_ports:
if clock_port not in ports:
print(f"{clock_port} ", end="")
if __name__ == "__main__":
main()
......@@ -37,7 +37,6 @@ if { [info exists ::env(MAX_TRANSITION_CONSTRAINT)] } {
configure_cts_characterization {*}$cts_characterization_args
puts "\[INFO]: Performing clock tree synthesis..."
puts "\[INFO]: Looking for the following net(s): $::env(CLOCK_NET)"
puts "\[INFO]: Running Clock Tree Synthesis..."
set arg_list [list]
......
# Copyright 2020-2022 Efabless Corporation
# Copyright 2020-2023 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
......@@ -11,7 +11,6 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
proc convert_pg_pins {lib_in lib_out} {
try_exec sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} $lib_in > $lib_out
}
......@@ -75,6 +74,22 @@ proc run_yosys {args} {
exec rm -f $arg_values(-output).bak
}
unset ::env(SAVE_NETLIST)
if { [info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != "" } {
set missing_clock_ports [exec\
python3 $::env(SCRIPTS_DIR)/check_clock_ports.py\
--top $::env(DESIGN_NAME)\
--netlist-in $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).json\
{*}$::env(CLOCK_PORT)]
set ports_not_found 0
foreach {clock_port} $missing_clock_ports {
puts_err "The specified clock port '$clock_port' does not exist in the top-level module."
set ports_not_found 1
}
if { $ports_not_found } {
throw_error
}
}
}
proc run_synth_exploration {args} {
......@@ -308,7 +323,7 @@ proc run_verilator {} {
lappend arg_list {*}$output_file
}
lappend arg_list {*}$::env(VERILOG_FILES)
set incdirs ""
if { [info exists ::env(VERILOG_INCLUDE_DIRS)] } {
foreach incdir $::env(VERILOG_INCLUDE_DIRS) {
......
......@@ -90,3 +90,4 @@ opt_clean -purge
tee -o "$::env(synth_report_prefix)$chk_ext" check
tee -o "$::env(synth_report_prefix)$stat_ext" stat -top $vtop -liberty $sclib
write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
write_json $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).json
......@@ -413,11 +413,14 @@ proc run_strategy {output script strategy_name {postfix_with_strategy 0}} {
autoname
}
set output_json $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).json
if { $postfix_with_strategy } {
set output "$output.$strategy_escaped.nl.v"
set output_json $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).$strategy_escaped.json
}
write_verilog -noattr -noexpr -nohex -nodec -defparam $output
write_json $output_json
design -reset
}
design -save checkpoint
......
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