Check if `CLOCK_PORT` is found in the design (#2074)
+ Add check for whether the ports listed under `CLOCK_PORT` in fact exist in the top-level module
- Remove misleading CTS log print
Co-authored-by:
Mohamed Gaber <donn@efabless.com>
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- designs/spm/config.json 1 addition, 1 deletiondesigns/spm/config.json
- scripts/check_clock_ports.py 32 additions, 0 deletionsscripts/check_clock_ports.py
- scripts/openroad/cts.tcl 0 additions, 1 deletionscripts/openroad/cts.tcl
- scripts/tcl_commands/synthesis.tcl 18 additions, 3 deletionsscripts/tcl_commands/synthesis.tcl
- scripts/yosys/elaborate.tcl 1 addition, 0 deletionsscripts/yosys/elaborate.tcl
- scripts/yosys/synth.tcl 3 additions, 0 deletionsscripts/yosys/synth.tcl
scripts/check_clock_ports.py
0 → 100644
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