Skip to content
Snippets Groups Projects
Select Git revision
  • master default protected
1 result
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.05Sep331Aug3022109331Jul2524191613121197626Jun22212019181514137631May30292824232218161110227Apr261918171613111065429Mar282723222116131175228Feb2622181375331Jan302524231918161110876228Dec27262221151312119543130Nov29282421181716151411109125Oct24232219181712953228Sep22201915127642131Aug292420181615929Jul27262522201918135126Jun232120181410754229May252117161196428Apr272618161514131176130Mar29282219181714119732128Feb252422201918171514139754231Jan302827262524212012109654331Dec3029282724232221201816151413987230Nov252423221918171615141312115128Oct27262522212019181716141312729Sep282219171698762131Aug30222118161596543130Jul282726721Jun18161510231May2118321Update OpenROAD + Handle Breaking Changes (#1949)SDC Behavior Overhaul (#1944)bump open_pdks version (#1969)Add Banner for OpenLane 2 (#1966)Partially Revert "Illegal Overlap Check Fix" (#1967)Illegal Overlap Check Fix (#1956)Overhaul Linter Handling of Black-boxed Verilog Models (#1929)Correct default value of `RUN_IRDROP_REPORT` in documentation (#1959)Update PDK + Restore `RC_LAYER` variables (#1932)`run_designs.py`: Fix `mkdirp` not being called in some scenarios (#1945)CI Tweaks (#1951)Revert "Enhancements to variables related to SDC files (#1931)"Enhancements to variables related to SDC files (#1931)Syntax Validation for IO and Macro Placement (#1938)Remove CTS_TOLERANCE (#1928)[BOT] Update PDK (#1869)OpenROAD python `read_def` api updates (#1926)Rename `mca` folders (#1922)[BOT] Update magic (#1914)Update Documentation (#1917)PIP Version Ranges (#1916)remove `unset_propagated_clock` (#1908)OR CI: consider that designs moved to submodule (#1900)Move CI designs to a separate repository (#1867)PDK Variable Consistency (#1892)Undocumented Variable CI WorkflowEnhance antenna violations report (#1893)Cleanup Deprecated Variable Documentation (#1887)Fix typo in usage of `RSZ_DONT_TOUCH` (#1885)Add missing documentation Fix lint errors in BM64 verilog sources (#1878)Always raise an exception when a design fails in the CI (#1879)Make synth checks more aggressive (#1880)irdrop.tcl bug fixes (#1882)Use OpenROAD mirror of `lemon-graph` (#1873)Enhance IR Drop Analysis (#1864)set MAGTYPE to mag for lef write as maglef is and abstract view and (#1859)Fix OpenROAD CI (#1868)Fix condition when RSZ_DONT_TOUCH_RX is defined (#1865)[BOT] Update PDK (#1834)