- Apr 26, 2017
-
-
ziheng authored
* [LANG] CommReducer * Reorganize c_api * Remove InitValue and Combine; refactor Functor * Make CommReducer an Expr * Make comm_reducer type independent * Make CommReducerNode a Node * Small fix * Refine * Refine front api; add integration testcases for min/max * Fix python * Refine * Fix lint and add example
-
Tianqi Chen authored
-
- Apr 25, 2017
-
-
Tianqi Chen authored
* [PASS] StorageRewrite, reuse memory pass as in NNVM. * fix issue
-
- Apr 22, 2017
-
-
Tianqi Chen authored
-
Tianqi Chen authored
* [LANG/CODEGEN] Intrinsics and Extern Math * fix lint
-
- Apr 21, 2017
-
-
Tianqi Chen authored
-
- Apr 20, 2017
-
-
Tianqi Chen authored
* [DOC] Scan tutorial * Fix according to ziheng's comment
-
- Apr 18, 2017
-
-
ziheng authored
* [DOC] Add schedule_computaion * Finetune the doc * Finetune the doc * Finetune the doc * Set max_unroll_step=0 by default
-
Tianqi Chen authored
-
Tianqi Chen authored
-
- Apr 17, 2017
-
-
Tianqi Chen authored
-
- Apr 16, 2017
-
-
Tianqi Chen authored
* [DOC] API doc organization. * remove breathe for now
-
- Apr 15, 2017
-
-
ziheng authored
* Add setup.py, fix comments * Update installation document
-
Tianqi Chen authored
* [DOC] Initial doc system * Migrate API * Update docs
-
Tianqi Chen authored
* [PERF] Persitent kernel * fix doc
-
- Apr 09, 2017
-
-
Tianqi Chen authored
* [SCHEDULE] Add group, refactor thread bind api. * fix doc * fix g++-4.8 * More testscase * Remove graph context from fix pt analysis
-
- Apr 01, 2017
-
-
Tianqi Chen authored
* [LANG/GPU] Cross Thread Reduction. * Fix doxygen error * Upgrade verilog testcase to new one
-
- Mar 29, 2017
-
-
Tianqi Chen authored
-
- Mar 26, 2017
-
-
Tianqi Chen authored
* [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place
-
- Mar 17, 2017
-
-
Tianqi Chen authored
* [VERILOG] VPI Mem Interface/ VPI MMap * fix test issues
-
- Mar 14, 2017
-
-
Tianqi Chen authored
* [RUNTIME] Refactor runtime to be DLPack compatible. Enable plugin of new runtime. * fix mac compile * ok
-
Tianqi Chen authored
* [VERILOG] Basic Verilog Testflow * fix build * fix the comment * fix lint in verilog
-
- Mar 12, 2017
-
-
Tianqi Chen authored
* [OP/LANG] Support Extern Call, more regression tests * [TEST] Include pylintrc
-
- Mar 07, 2017
-
-
Tianqi Chen authored
-
- Mar 05, 2017
-
-
Tianqi Chen authored
* [IterVar/REFACTOR] Add types to IterVar * [ARITH/REFACTOR] Move IntSet to include * [REFACTOR/OP] Move Op detail to seperate folder. * fix test
-
- Mar 01, 2017
-
-
Tianqi Chen authored
* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor * retrigger * [IRFunctor] Migrated CodegenC * [IRFUNCTOR] Migrate CodeGenLLVM * [IRFunctor] Migrate canonical * [IRFunctor] Migrate vectorize * [IRFunctor] migrate CodeGenStackVM
-
- Feb 27, 2017
-
-
Tianqi Chen authored
-
- Feb 26, 2017
-
-
Tianqi Chen authored
-
Tianqi Chen authored
-
- Feb 24, 2017
-
-
Tianqi Chen authored
-
- Feb 22, 2017
-
-
Tianqi Chen authored
* [LLVM] Initial support for codegen LLVM. * Fix the naming issue of codegen
-
- Feb 20, 2017
-
-
Tianqi Chen authored
-
- Feb 17, 2017
-
-
Ziheng Jiang authored
* [PYTHON/API] Add compare and logic build-in op for Expr * remove 'and', 'or' * add deducer * [WIP] bound_deducer.cc * move IntervalSet and StrideSet into int_set_internal.h * add multiple failure for VariablePathFinder, add EvalSign * consider round in deduce, add success flag * remove Visit_(Div) * add comment, update HalideIR * expose intset to python * check the sign of every expr * set return type as ExprSignType * fine tune * add min & max python api for interval set * support for conditional expr * refactor test * add checker for BoundDeducer * add python check test * fix * fix * change range to interval; remove converter * remove converter declaration * remove int_set_internal.h
-
Tianqi Chen authored
-
- Feb 14, 2017
-
-
Tianqi Chen authored
-
- Feb 11, 2017
-
-
Tianqi Chen authored
-
- Feb 10, 2017
-
-
Ziheng Jiang authored
* [PYTHON/API] Add compare and logic build-in op for Expr * remove 'and', 'or'
-
- Feb 09, 2017
-
-
Tianqi Chen authored
-
Ziheng Jiang authored
* [FUSION] add Fusion(Schedule) * [FUSION] rename to AutoFuseEwise, detect whether the stage has been scheduled * [FUSION] change to visitor pattern * [FUSION] rename filename * [FUSION] fine-tune the interface * [FUSION] typo * move elem_wise to schedule * rename test function
-
- Feb 07, 2017
-
-
Tianqi Chen authored
-