* [SCHEDULE][PASS] Enable Warp memory and lower to shuffle

* OpenCL dispatches for now to intel shuffle

* [SCHEDULE]enable partition const loop with build flag (#719)

    * enable partition loop with build flag

    * add a testcase, and modify LoopPartition related cases

*     * add document for split_const_loop

* [PASS/SETUP] Fix minior issues

* fix lint

* [PASS] copy intrin

* update comment thanks to derisavi

* [PASS] Refactor thread storage sync to a common visitor

* Fix the sync scope check behavior

* [STORAGE][BUFFER] Support access ptr for clear access pattern.

* fix lint

* prefetch interface added

* prefetch python comments modified. prefetch info data structure maintained.

* start injecting prefetches. first step (domain touch) implemented.

* domain touch tested.

* Prefetch ir_mutator and ir_visitor dispatch registered.

* modify domain touched from passing a func_ref to passing a tensor

* modify domain touched from passing a func_ref to passing a tensor

* modify Tensor copy to Tensor ref

* temp commit for rebase

* debug info removed, typo fixed, ready to rebase

* prefetch flatten test add!

* roll back builtin functions to side effect functions

* lint error fixed!

* add cache line size to storage flatten argument

* forgot modifications add

* change code style to dmlc-like; get rid of can_prove, use manually compute instead

* python lint error fixed

* modify instrinsic name to pass tests

* [TEST] get rid of str(), replace them by accessing attributes

* change map to list comprehension

* redundant numpy import removed

* [RUNTIME] Add workspace pool

* fix doc

* fix the free list

* avoid zero size

* [CODEGEN/PASS] add restricted, alignment option

* fix lint

* Fix the alloca

* [REFACTOR/PASS] Formalize argument bind and match util

* grammar

* [CODEGEN/PASS] Improve callpacked lowering, allow pass array callback.

* fix cython

* [PASS] StorageRewrite, reuse memory pass as in NNVM.

* fix issue

* [LANG/CODEGEN] Intrinsics and Extern Math

* fix lint

* [LANG/GPU] Cross Thread Reduction.

* Fix doxygen error

* Upgrade verilog testcase to new one

* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place

* loop_partition draft

* divide loop variable into constant domain and variable domain & consider multiple partitions

* process doubt interval

* fix and refactor, add relax_map arg in BoundDeduce

* fix testcase and comment

* rebase to zero, convert to SSA

* change the logic of generating loop code & fix issues

* add a testcase for relax map in deducebound && fix issues

* clean code

* const auto&

* add test_multi_if