* Support vector operations for AMD (llvm IR)

* fix whitespace

* update comments, docstring

Change minimum 32-bit restriction for floating point types to 8-bit.
This change is to enable reduced precision types that may use vector operations underneath the hood (cases #lanes > 1 such as half4).

* enable popcount intrin

* fix lint

* add test

* fix python3

* removed fma dispatch

* added comments to explain why remove fma

* fix lint

* use fmuladd intrin for fma dispatch

* view llvm ir and gcn asm with module.get_source(...)

* fix lint

* [BUFFER] Smarter slice to detect compactness

* move simplify of begins early

* added math function support

* bug fix extern func call in llvm based codegen

lint fix

fix build

bug fix extern func call in llvm based codegen

* moved rocm bitcodes detection to python

* [ARITH] More caninical simplfy

* [DEBUG] Use HalideIR with trace logging

* [CODEGEN] Allow link additional module

* fix py3

* add register back

* [CODEGEN] Force not inline compute core for better debug

* also support llvm4

* [TVM] Introduce target generic dispatch system

* fix target warning

* [CODEGEN] Detect broadcast(cast(x)) pattern in FMA

* [CODEGEN] Improve

* [CODEGEN] Fix

* added support for rocm gpu autodetect

* changed type casting from old style to static_cast

* fixed code to generate gfx specific code object

* fixed namespaces

* [RUNTIME] Enable ext_dev type for quick plugin of device

* [TEST] Update testcase to cover all computation

* [PASS] copy intrin

* update comment thanks to derisavi

* [ARITH] Improve detect linear equation

* fix doc

* [RUNTIME] Minimum graph runtime

* update docs

* [INTRIN] Enable pow

* rename pow->power

* fix

* [CODEGEN] Redo CodegenLLVM.

* Add remarks about origin of the pass

Properly acknowledge related projects

* Fix and expression

* [METAL] use 32bit indexing for metal until we have a bound adapted pass

* fix lint