* [PASS] StorageRewrite, reuse memory pass as in NNVM.

* fix issue

* [LANG/CODEGEN] Intrinsics and Extern Math

* fix lint

* [LANG/GPU] Cross Thread Reduction.

* Fix doxygen error

* Upgrade verilog testcase to new one

* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place

* loop_partition draft

* divide loop variable into constant domain and variable domain & consider multiple partitions

* process doubt interval

* fix and refactor, add relax_map arg in BoundDeduce

* fix testcase and comment

* rebase to zero, convert to SSA

* change the logic of generating loop code & fix issues

* add a testcase for relax map in deducebound && fix issues

* clean code

* const auto&

* add test_multi_if

* [API] Move all RTTI related code to one place

* add back rtti comment

* [PASS] Assign unique names to variables in ConvertSSA pass

* revert change to ConverSSA pass

* [PASS] Export simplify and equal to python

* fix naming convention

* [PASS] Schedule Ops init working version

* bugfix in PassUp