* [CONTRIB/BLAS] Add CBLAS Example to contrib

* Update makefile

* [CODEGEN/RUNTIME] Metal support, runtime improvement.

* Fix case when no device is available

* [CODEGEN/PASS] Improve callpacked lowering, allow pass array callback.

* fix cython

* [DOC] Add intro to 'comm_reducer' in tutorial; fix doc

* Fix

* Fix

* [PYTHON/FFI] Enable Cython FFI

* fix cython

* [LANG] CommReducer

* Reorganize c_api

* Remove InitValue and Combine; refactor Functor

* Make CommReducer an Expr

* Make comm_reducer type independent

* Make CommReducerNode a Node

* Small fix

* Refine

* Refine front api; add integration testcases for min/max

* Fix python

* Refine

* Fix lint and add example

* [PASS] StorageRewrite, reuse memory pass as in NNVM.

* fix issue

* [LANG/CODEGEN] Intrinsics and Extern Math

* fix lint

* [PERF] Persitent kernel

* fix doc

* [SCHEDULE] Add group, refactor thread bind api.

* fix doc

* fix g++-4.8

* More testscase

* Remove graph context from fix pt analysis

* [LANG/GPU] Cross Thread Reduction.

* Fix doxygen error

* Upgrade verilog testcase to new one

* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place

* [VERILOG] VPI Mem Interface/ VPI MMap

* fix test issues

* [RUNTIME] Refactor runtime to be DLPack compatible. Enable plugin of new runtime.

* fix mac compile

* ok

* [VERILOG] Basic Verilog Testflow

* fix build

* fix the comment

* fix lint in verilog

* [OP/LANG] Support Extern Call, more regression tests

* [TEST] Include pylintrc

* [IterVar/REFACTOR] Add types to IterVar

* [ARITH/REFACTOR] Move IntSet to include

* [REFACTOR/OP] Move Op detail to seperate folder.

* fix test

* loop_partition draft

* divide loop variable into constant domain and variable domain & consider multiple partitions

* process doubt interval

* fix and refactor, add relax_map arg in BoundDeduce

* fix testcase and comment

* rebase to zero, convert to SSA

* change the logic of generating loop code & fix issues

* add a testcase for relax map in deducebound && fix issues

* clean code

* const auto&

* add test_multi_if

* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor

* retrigger

* [IRFunctor] Migrated CodegenC

* [IRFUNCTOR] Migrate CodeGenLLVM

* [IRFunctor] Migrate canonical

* [IRFunctor] Migrate vectorize

* [IRFunctor] migrate CodeGenStackVM

* [LLVM] Initial support for codegen LLVM.

* Fix the naming issue of codegen

* [PASS] Change IRVisitor interfaces to function override

* [PASS] Change IRMutator interfaces to overloadable function

* [FUSION] add Fusion(Schedule)

* [FUSION] rename to AutoFuseEwise, detect whether the stage has been scheduled

* [FUSION] change to visitor pattern

* [FUSION] rename filename

* [FUSION] fine-tune the interface

* [FUSION] typo

* move elem_wise to schedule

* rename test function