do update_fpsb_idx from hw irq handler before re-enabling NIC INTR, and do not
run this update function from bnx2x_poll while we are running our enforcement
module. this seems to reduce the number of hw interrupts generated, since now
the NIC does not think that the previous set of pkts have not been acknowledged
by the driver.

an attempt to reduce extra pointer accesses that may affect cache misses or TLB
misses

(1) has_rx_work based on hwi* and swi* indexes under sme module
(2) do not goto redo_poll, instead let net_rx_action and napi_poll handle
invocation of bnx2x_poll again
(3) update swi* to same values as rx* at the end of __bnx2x_rx_int, else causes
issues upon rmmod sme module

bugfix: index overflow, handle case where producer index wraps around and becomes smaller than consumer index

bugfix: hwi* and swi* indexes should not be set to modulus of ring buffer size, but allow incrementing freely

(1) enable intr at exit from hwirq handler; (2) put all code under module load check; (3) use hwi\* and swi\* indexes only with enforcement; (4) do not update hwi\* indexes in swirq handler with module loaded

add code to check the queues after napi_complete once more; and redo bnx2x_rx_int work if new data added (no change to hw irq handler)

change NAPI budget; timestamp in hwirq; modify poll function to enable interrupt after every rcv pkt processing