+ Repository is now a Nix flake
~ Change all invocations of `openroad -python` to use `run_odbpy_script` for consistency
~ Change build system from ad-hoc to Nix, still producing a Docker image as a final result
~ Update KLayout scripts to use `klayout-pymod` or properly parse commandline arguments
~ `open_pdks` -> `bdc9412` to match OpenLane 2
- Remove local installer; `nix run .` will run OpenLane natively

~ `openroad_app` -> `da0053d` to fix an issue with antenna repair

~ `openroad_app` -> `0889970`
~ `scripts/odbpy/reader.py`: Added workaround to continue to be able to use multiple DBs, See https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4743 for more info

~ openroad_app -> `75f2f32`

## CI
~ Always compare regression and create reproducibles
~ Always escape design name
+ Add tests for attached crashes by adding issues reproducibles in designs submodules and symlink them to interactive scripts under ./tests
+ Fix failing designs in extended test:
  * salsa20: setup violations
  * y_huff: routing congestion
  * aes_core: pin antenna violations benchmark mismatch

~ Bump open_pdks version to `cd1748bb197f9b7af62a54507de6624e30363943`
~ Rename `PRIMARY_SIGNOFF_TOOL` to `PRIMARY_GDSII_STREAMOUT_TOOL`
~ Update documentation of `RUN_MAGIC_DRC` and `RUN_KLAYOUT_DRC`
+ Integrate KLayout DRC for sky130
+ Add the following variables:
```
KLAYOUT_DRC_THREADS
QUIT_ON_KLAYOUT_DRC
RUN_KLAYOUT_DRC
KLAYOUT_DRC_RUNSET - PDK variable
KLAYOUT_DRC_OPTIONS - PDK variable
```
- Remove `KLAYOUT_DRC_KLAYOUT_GDS`

~ `open_pdks` -> `e0f692f` to match https://github.com/efabless/openlane2/pull/275

~ `openroad_app` -> `6f9b2bb` to match efabless/openlane2#255

~`verilator` -> `67dfa37`

~ Yosys -> `0.34`

~ `openroad_app` -> `0a584d1`

* Update OpenROAD to `bdc8e94`

~ `open_pdks` -> `dd7771c384ed36b91a25e9f8b314355fc26561be`

- Remove `cvc_rv` utility (upstream no longer willing to support it as part of the flow)
~ Fix bug with OpenLane docker image builder copying run folders

+ update utils.py `fetch_submodules_from_tarballs` to handle relative submodule url
~ `openroad_app` -> `0a6d0fd`
~ add extractor for operating conditions  

Co-authored-by: Donn <me@donn.website>

```
~ Correct feedback file in `extract_spice`
~ `open_pdks` -> `1341f54`
```

~ `open_pdks` -> `e3b630d9b7c0e23615367d52c4f78b2d2ede58ac`
~ `WIRE_RC_LAYER` split back into `CLOCK_WIRE_RC_LAYER` and `DATA_WIRE_RC_LAYER`

Co-authored-by: Mohamed Gaber <me@donn.website>

open_pdks -> 933e5f2b8e42c5ec25b83c6d242455ada6f3e926

~ bump openroad version
~ update openroad python odb read_def api usage to pass tech instead of odb object based on https://github.com/The-OpenROAD-Project/OpenLane/issues/1925

Merging to avoid bug with 8.3.412-8.3.415

~ Classified PDK variables by user modifiability
~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT`
~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT`
~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD`
- Removed `DEFAULT_MAX_TRAN` from PDK (unused)

~ move synth check before opt to capture more errors
~ bump yosys version to address more cases of synth checks. see attached issue link

open_pdks -> 3df14f84ab167baf757134739bb1d2c5c044849c

magic -> 482d7534a27c51d0d1c8a466494680d185d334ee

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
Co-authored-by: Kareem Farid <kareefardi@users.noreply.github.com>

~ default to lef/def in order to generate lef with pin direction (and much faster than gds) 
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation

openroad_app -> ceae0ad175e8b0183c3a64af79ba18139dcda63a

openroad_app -> 9a713f0e8a51769207918da28adfd3c02b854375

This reverts commit 541c9595.

~ `openroad` -> `e289bc2ce4fee72a5d3e240d1b61b6385fcbe807`

magic -> c514f5ce0b9407372d05d98bcb2984f3fe0829f8

openroad_app -> 7f6c37aa57467242807155c654deb350022d75c1

open_pdks -> af3485525297d5cbe93c129ea853da2d588fac41

magic -> a33d7b78b54d8456769d08236f91f9be31784267

openroad_app -> 9f09183daeee711a13b01122b11358b935ade288

Renamed Variables:
```
CLOCK_TREE_SYNTH -> RUN_CTS
FP_PDN_RAILS_LAYER -> FP_PDN_RAIL_LAYER
FP_PDN_UPPER_LAYER, FP_PDN_LOWER_LAYER -> FP_PDN_HORIZONTAL_LAYER, FP_PDN_VERTICAL_LAYER
```
Removed from default configuration:
```
RCX_CORNER_COUNT
RCX_MAX_RESISTANCE		
RCX_COUPLING_THRESHOLD		
RCX_CC_MODEL	
RCX_CONTEXT_DEPTH
```
Added documentation:
```
FP_PDN_CFG
FP_PDN_HSPACING
FP_PDN_VSPACING
FP_TAPCELL_DIST
DFF_LIB_SYNTH
DIODE_CELL_PIN
DIODE_CELL
STD_CELL_GROUND_PINS
CARRY_SELECT_ADDER_MAP
FULL_ADDER_MAP
STD_CELL_LIBRARY_CDL
LAYERS_RC
VIAS_RC
SYNTH_DEFINES
STA_REPORT_POWER
FP_PDN_ENABLE_GLOBAL_CONNECTIONS
PL_RESIZER_TIE_SEPERATION
QUIT_ON_HOLD_VIOLATIONS
QUIT_ON_SETUP_VIOLATIONS
QUIT_ON_TIMING_VIOLATIONS
```
Moved to pdk configuration:
```
FP_PDN_VOFFSET
FP_PDN_VPITCH
FP_PDN_HOFFSET
FP_PDN_HPITCH
```
\- Remove unneeded usage of `PL_TARGET_DENSITY_CELLS`

Addresses https://github.com/The-OpenROAD-Project/OpenLane/issues/1325

+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD