* [CONTRIB/BLAS] Add CBLAS Example to contrib

* Update makefile

* adding tvm_buffer and fifo testbench

* minor edits

* line buffer test bench

* adding double buffer tests for the tvm_buffer

* making variable consistent with  python style

* [CODEGEN] Refactor common codegen, Verilog Codegen

* fix make

* fix mk

* update enable signal

* change function name to at neg edge

* Move test to correct place

* [VERILOG] VPI Mem Interface/ VPI MMap

* fix test issues

* [VERILOG] Basic Verilog Testflow

* fix build

* fix the comment

* fix lint in verilog