~ use tclmodules (`.tm`) files instead of pkgIndex.tcl for openlane and openlane_utils
~ change tagging to use the version from the `.tm` files instead of the day of the release
~ include superstable branch in tagging efforts (even though this doesn't mean much in `master`…)

~ `openlane2` -> `2.1.3`
~ use known-good version of OpenSTA: see https://github.com/parallaxsw/OpenSTA/issues/82
   ~ version linked against OpenROAD not affected

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>

* Synchronize tool versions with OpenLane 2.1.1.
* Downgrade Magic to 8.3.478: See https://github.com/RTimothyEdwards/magic/issues/317
* Purge `odb.dbDatabase.create` from the codebase: See https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4743

Signed-off-by: Mohamed Gaber <donn@efabless.com>

+ Add conditional `set_propagated_clocks` for all clocks in `base.sdc`
  ~ Condition is true for:
    ~ CTS STA
    ~ Global routing STA
    ~ Global routing optimizations STA
    ~ Multicorner(signoff) STA
+ Add conditional `set_propagated_clocks` for all clocks after reading an sdc file depending on whether the statement is used in the sdc file for not. Idea is to be backwards compatible with the default behavior of OpenLane of propagating clocks _outside_ the sdc file
+ Add a report for non-propagated clocks
+ Add a report for information regarding clocks 

~ Fixed generation for the following metrics:
  ~ Power values
  ~ `critical_path_report`
  ~ some wns and tns values
  ~ klayout drc
- Remove CVC Metrics

~ Increases banner size for OpenLane 2, now uses a PNG rendered at 1200 API on macOS for consistency
~ Updated Flow Architecture Document

Co-authored-by: Mohamed Gaber <donn@efabless.com>

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>

~ Avoid using `/dev/null` for writing DEF files (it tries to create a temp file and fail)
~ PDK now has a default value of sky130A even outside the Makefile
~ PDK_ROOT now set automatically if Volare is installed
~ Upgrade to a newer version of OpenLane 2, which in turns uses `nix-eda` 
~ Format nix packages using Alejandra
~ OpenROAD scripts now read liberty files before database files (they are linked together when the database is read)
~ Update Readme to remove Colab and add banner directing people to OpenLane 2

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>

- Remove `LEC_ENABLE` and `logic_equiv_check`

+ Repository is now a Nix flake
~ Change all invocations of `openroad -python` to use `run_odbpy_script` for consistency
~ Change build system from ad-hoc to Nix, still producing a Docker image as a final result
~ Update KLayout scripts to use `klayout-pymod` or properly parse commandline arguments
~ `open_pdks` -> `bdc9412` to match OpenLane 2
- Remove local installer; `nix run .` will run OpenLane natively

~ `openroad_app` -> `da0053d` to fix an issue with antenna repair

~ Fixed exit codes not being propagated for tools that get automatic reproducible creation

~ Clock port check at beginning of flow now allows bits of a bus to be used as clock portss
~ Clock port check at beginning of flow no longer allows outputs to be used as clock ports

+ Always read `LIB_SYNTH_COMPLETE` in Yosys scripts
- Remove `SYNTH_READ_BLACKBOX_LIB`

~ Add -defer to `read_verilog` commands in Yosys; only elaborating after all files are read
~ Run hierarchy after `read_verilog` for elaboration as well

~ `openroad_app` -> `0889970`
~ `scripts/odbpy/reader.py`: Added workaround to continue to be able to use multiple DBs, See https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4743 for more info

I worked on adding documentation to OpenLane in Spanish using a more visually appealing website, and providing a translation of the openlane configuration parameters. 
I only updating the link, the website used to come from "erickcb", my personal github account, but it is now from "lima-ucr", the account for the laboratory I run at Universidad de Costa Rica

Signed-off-by: Laboratorio de Investigación en Microelectrónica y Arquitectura de Computadoras, EIE -- UCR <135917299+lima-ucr@users.noreply.github.com>

~ openroad_app -> `75f2f32`

## CI
~ Always compare regression and create reproducibles
~ Always escape design name
+ Add tests for attached crashes by adding issues reproducibles in designs submodules and symlink them to interactive scripts under ./tests
+ Fix failing designs in extended test:
  * salsa20: setup violations
  * y_huff: routing congestion
  * aes_core: pin antenna violations benchmark mismatch

+ Add check for whether the ports listed under `CLOCK_PORT` in fact exist in the top-level module
- Remove misleading CTS log print

Co-authored-by: Mohamed Gaber <donn@efabless.com>

Co-authored-by: Mohamed Gaber <donn@efabless.com>

~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
    ~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
    ~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
    ~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)

~ Add submodules to ReadTheDocs builds, as there are references to files in submodules (CI configurations, netlists, etc)

STA black-boxing no longer warns about any cells in `FILL_CELL`, `DECAP_CELL` and `FP_WELLTAP_CELL`. The aim of this is to try to minimize frivolous warnings so that users don't miss other important warnings.

+ Also indicate in the logs if `skip_io` was passed to global placement.